By Frank Hannig, João M.P. Cardoso, Thilo Pionteck, Dietmar Fey, Wolfgang Schröder-Preikschat, Jürgen Teich
This e-book constitutes the court cases of the twenty ninth foreign convention on structure of Computing platforms, ARCS 2016, held in Nuremberg, Germany, in April 2016.
The 29 complete papers awarded during this quantity have been rigorously reviewed and chosen from 87 submissions. They have been geared up in topical sections named: configurable and in-memory accelerators; network-on-chip and safe computing architectures; cache architectures and protocols; mapping of purposes on heterogeneous architectures and real-time projects on multiprocessors; all approximately time: timing, tracing, and function modeling; approximate and energy-efficient computing; allocation: from thoughts to FPGA modules; natural computing platforms; and reliability elements in NoCs, caches, and GPUs.
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Additional info for Architecture of Computing Systems -- ARCS 2016: 29th International Conference, Nuremberg, Germany, April 4-7, 2016, Proceedings
For this reason they make more sense in a near-memory processor. We have augmented PIM with a DMA engine capable of bulk data transfers between the DRAM vaults and its SPM (See Fig. 1a). It allows multiple outstanding transactions by having several DMA resources, and accepts virtual address ranges without any alignment or size restrictions. A complementary way to address this problem is to move some very speciﬁc arithmetic operations directly to the DRAM dies and ask the vault controller to do them “atomically”.
Power consumed in the DRAM devices was extracted from DRAMPower . 75 pJ/bit . SMC Controller was estimated to consume 10 pj/bit by scaling values obtained in . 9 Watts (for transmission of the null ﬂits) was estimated based on the maximum power reported in  and link eﬃciency in . Also, since power state transition for the serial links introduces long sleep latency in the order of a few hundred nanoseconds, and a wakeup latency of a few microseconds , we assumed that during host’s computations, links are 28 E.
Hardware coherence is maintained with the host and virtual memory support has been provided. 2X performance improvement is reported for dense matrix operations, increasing to 5X when vicinity aware memory allocation is utilized. Tesseract  features a network of memory cubes each accommodating 32 in-order cores with L1 caches and two prefetchers, optimized for parallelizing the PageRank algorithm. Uncacheable regions are shared with PIM and segmented memory without paging is supported. Up to 10X performance improvement and 87 % energy reduction has been provided in comparison with high-performance server hosts.
Architecture of Computing Systems -- ARCS 2016: 29th International Conference, Nuremberg, Germany, April 4-7, 2016, Proceedings by Frank Hannig, João M.P. Cardoso, Thilo Pionteck, Dietmar Fey, Wolfgang Schröder-Preikschat, Jürgen Teich